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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 1-/2-/4-channel digital potentiometers ad8400/ad8402/ad8403 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 features 256 position replaces 1, 2 or 4 potentiometers 1 k v , 10 k v , 50 k v , 100 k v power shut downless than 5 m a 3-wire spi compatible serial data input 10 mhz update data loading rate +2.7 v to +5.5 v single-supply operation midscale preset applications mechanical potentiometer replacement programmable filters, delays, time constants volume control, panning line impedance matching power supply adjustment functional block diagram rdac1 shdn 8 8-bit latch ck rs rdac2 shdn 8 8-bit latch ck rs rdac3 shdn 8 8-bit latch ck rs rdac4 shdn 8 8-bit latch ck rs shdn dac select a1, a0 1 2 3 4 10-bit serial latch ck q rs d rs sdo a1 w1 b1 agnd1 a2 w2 b2 agnd2 a3 w3 b3 agnd3 a4 w4 b4 agnd4 ad8403 v dd dgnd sdi clk cs 8 2 general description the ad8400/ad8402/ad8403 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (vr) device. these devices perform the same electronic adjustment function as a potentiometer or variable resistor. the ad8400 contains a single variable resistor in the compact so-8 package. the ad8402 contains two independent variable resistors in space saving so-14 surface mount package. the ad8403 con- tains four independent variable resistors in 24-lead pdip, soic and tssop packages. each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point deter- mined by a digital code loaded into the controlling serial input register. the resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the vr latch. each variable resistor offers a completely programmable value of resistance, between the a terminal and the wiper or the b terminal and the wiper. the fixed a to b terminal resistance of 1 k w , 10 k w , 50 k w or 100 k w has a 1% channel- to-ch annel matching tolerance with a nominal temperature coefficient of 500 ppm/ c. a unique switching cir- cuit minimizes the high glitch inherent in traditional switched resistor d esigns avoiding any make-before-break or break-before- make operation. each vr has its own vr latch that holds its programmed resistance value. these vr latches are updated from an spi compatible serial-to-parallel shift register that is loaded from a standard 3- wire serial-input digital interface. ten data bits make up the data word clocked into the serial input register. the data word is decoded where the first two bits determine the address of the vr latch to be loaded, the last eight bits are data. a serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple vr applications without addi- tional external decoding logic. the reset ( rs ) pin forces the wiper to the midscale position by loading 80 h into the vr latch. the shdn pin forces the resis- tor to an end-to-end open circuit condition on the a terminal and shorts the wiper to the b terminal, achieving a microwatt power shutdown state. when shdn is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. the digital interface is still active in shutdown so that code changes can be made which will produce new wiper positions when the device is taken out of shutdown. the ad8400 is available in both the so-8 surface mount and the 8-lead plastic dip package. the ad8402 is available in both surface mount (so-14) and the 14-lead plastic dip package, while the ad8403 is available in a narrow body 24-lead plastic dip and the 24-lead surface mount package. the ad8402/ad8403 are also offered in the 1.1 mm thin tssop-14/tssop-24 package for pcmcia ap- plications. all parts are guaranteed to operate over the extended industrial temperature range of C40 c to +85 c.
10 k v version electrical characteristics parameter symbol conditions min typ 1 max units dc characteristics rheostat mode specifications apply to all vrs resistor differential nl 2 r-dnl r wb , v a = nc C1 1/4 +1 lsb resistor nonlinearity 2 r-inl r wb , v a = nc C2 1/2 +2 lsb nominal resistance 3 rt a = +25 c, model: ad840xyy10 8 10 12 k w resistance tempco d r ab / d tv ab = v dd , wiper = no connect 500 ppm/ c wiper resistance r w i w = 1 v/r 50 100 w nominal resistance match d r/r o ch 1 to 2, 3, or 4, v ab = v dd , t a = +25 c 0.2 1 % dc characteristics potentiometer divider specifications apply to all vrs resolution n 8 bits integral nonlinearity 4 inl C2 1/2 +2 lsb differential nonlinearity 4 dnl v dd = +5 v C1 1/4 +1 lsb dnl v dd = +3 v t a = +25 cC1 1/4 +1 lsb dnl v dd = +3 v t a = C40 c, +85 c C1.5 1/2 +1.5 lsb voltage divider tempco d v w / d t code = 80 h 15 ppm/ c full-scale error v wfse code = ff h C4 C2.8 0 lsb zero-scale error v wzse code = 00 h 0 +1.3 +2 lsb resistor terminals voltage range 5 v a, b, w 0v dd v capacitance 6 ax, bx c a, b f = 1 mhz, measured to gnd, code = 80 h 75 pf capacitance 6 wx c w f = 1 mhz, measured to gnd, code = 80 h 120 pf shutdown current 7 i a_sd v a = v dd , v b = 0 v, shdn = 0 0.01 5 m a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = +5 v 100 200 w digital inputs & outputs input logic high v ih v dd = +5 v 2.4 v input logic low v il v dd = +5 v 0.8 v input logic high v ih v dd = +3 v 2.1 v input logic low v il v dd = +3 v 0.6 v output logic high v oh r l = 1 k w to v dd v dd C0.1 v output logic low v ol i ol = 1.6 ma, v dd = +5 v 0.4 v input current i il v in = 0 v or +5 v, v dd = +5 v 1 m a input capacitance 6 c il 5pf power supplies power supply range v dd range 2.7 5.5 v supply current (cmos) i dd v ih = v dd or v il = 0 v 0.01 5 m a supply current (ttl) 8 i dd v ih = 2.4 v or 0.8 v, v dd = +5.5 v 0.9 4 ma power dissipation (cmos) 9 p diss v ih = v dd or v il = 0 v, v dd = +5.5 v 27.5 m w power supply sensitivity pss v dd = +5 v 10% 0.0002 0.001 %/% pss v dd = +3 v 10% 0.006 0.03 %/% dynamic characteristics 6, 10 bandwidth C3 db bw_10k r = 10 k w 600 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, v b = 2 v dc, f = 1 khz 0.003 % v w settling time t s v a = v dd , v b = 0 v, 1% error band 2 m s resistor noise voltage e nwb r wb = 5 k w , f = 1 khz, rs = 0 9 nv/ ? hz crosstalk 11 c t v a = v dd , v b = 0 v C65 db notes for 10 k w version 1 typicals represent average readings at +25 c and v dd = +5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. see figure 30 test circuit. i w = 50 m a for v dd = +3 v and i w = 400 m a for v dd = +5 v for the 10 k w versions. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see figure 29 test circuit. 5 resistor terminals a, b, w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on the measured terminal. the remaining resistor terminals are left open circuit. 7 measured at the ax terminals. all ax terminals are open circuited in shutdown mode. 8 worst case supply current consumed when input logic level at 2.4 v, standard characteristic of cmos logic. see figure 21 for a plot of i dd versus logic voltage. 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = +5 v. 11 measured at a v w pin where an adjacent v w pin is making a full-scale voltage change. specifications subject to change without notice. ad8400/ad8402/ad8403Cspecifications (v dd = +3 v 6 10% or + 5 v 6 10%, v a = +v dd , v b = 0 v, C40 8 c t a +85 8 c unless otherwise noted) rev. b C2C
50 k v & 100 k v version electrical characteristics parameter symbol conditions min typ 1 max units dc characteristics rheostat mode specifications apply to all vrs resistor differential nl 2 r-dnl r wb , v a = nc C1 1/4 +1 lsb resistor nonlinearity 2 r-inl r wb , v a = nc C2 1/2 +2 lsb nominal resistance 3 rt a = +25 c, model: ad840xyy50 35 50 65 k w rt a = +25 c, model: ad840xyy100 70 100 130 k w resistance tempco d r ab / d tv ab = v dd , wiper = no connect 500 ppm/ c wiper resistance r w i w = 1 v/r 53 100 w nominal resistance match d r/r o ch 1 to 2, 3, or 4, v ab = v dd , t a = +25 c 0.2 1 % dc characteristics potentiometer divider specifications apply to all vrs resolution n 8 bits integral nonlinearity 4 inl C4 1 +4 lsb differential nonlinearity 4 dnl v dd = +5 v C1 1/4 +1 lsb dnl v dd = +3 v t a = +25 cC1 1/4 +1 lsb dnl v dd = +3 v t a = C40 c, +85 c C1.5 1/2 +1.5 lsb voltage divider tempco d v w / d t code = 80 h 15 ppm/ c full-scale error v wfse code = ff h C1 C0.25 0 lsb zero-scale error v wzse code = 00 h 0 +0.1 +1 lsb resistor terminals voltage range 5 v a, b, w 0v dd v capacitance 6 ax, bx c a, b f = 1 mhz, measured to gnd, code = 80 h 15 pf capacitance 6 wx c w f = 1 mhz, measured to gnd, code = 80 h 80 pf shutdown current 7 i a_sd v a = v dd , v b = 0 v, shdn = 0 0.01 5 m a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = +5 v 100 200 w digital inputs & outputs input logic high v ih v dd = +5 v 2.4 v input logic low v il v dd = +5 v 0.8 v input logic high v ih v dd = +3 v 2.1 v input logic low v il v dd = +3 v 0.6 v output logic high v oh r l = 1 k w to v dd v dd C0.1 v output logic low v ol i ol = 1.6 ma, v dd = +5 v 0.4 v input current i il v in = 0 v or +5 v, v dd = +5 v 1 m a input capacitance 6 c il 5pf power supplies power supply range v dd range 2.7 5.5 v supply current (cmos) i dd v ih = v dd or v il = 0 v 0.01 5 m a supply current (ttl) 8 i dd v ih = 2.4 v or 0.8 v, v dd = +5.5 v 0.9 4 ma power dissipation (cmos) 9 p diss v ih = v dd or v il = 0 v, v dd = +5.5 v 27.5 m w power supply sensitivity pss v dd = +5 v 10% 0.0002 0.001 %/% pss v dd = +3 v 10% 0.006 0.03 %/% dynamic characteristics 6, 10 bandwidth C3 db bw_50k r = 50 k w 125 khz bw_100k r = 100 k w 71 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, v b = 2 v dc, f = 1 khz 0.003 % v w settling time t s _50k v a = v dd , v b = 0 v, 1% error band 9 m s t s _100k v a = v dd , v b = 0 v, 1% error band 18 m s resistor noise voltage e nwb _50k r wb = 25 k w , f = 1 khz, rs = 0 20 nv/ ? hz e nwb _100k r wb = 50 k w , f = 1 khz, rs = 0 29 nv/ ? hz crosstalk 11 c t v a = v dd , v b = 0 v C65 db notes for 50 k w and 100 k w versions 1 typicals represent average readings at +25 c and v dd = +5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. see figure 30 test circuit. i w = v dd /r for v dd = +3 v or +5 v for the 50 k w and 100 k w versions. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see figure 29 test circuit. 5 resistor terminals a, b, w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on the measured terminal. the remaining resistor terminals are left open circuit. 7 measured at the ax terminals. all ax terminals are open circuited in shutdown mode. 8 worst case supply current consumed when input logic level at 2.4 v, standard characteristic of cmos logic. see figure 21 for a plot of i dd versus logic voltage. 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = +5 v. 11 measured at a v w pin where an adjacent v w pin is making a full-scale voltage change. specifications subject to change without notice. ad8400/ad8402/ad8403 rev. b C3C (v dd = +3 v 6 10% or + 5 v 6 10%, v a = +v dd , v b = 0 v, C40 8 c t a +85 8 c unless otherwise noted) specifications
1 k v version electrical characteristics parameter symbol conditions min typ 1 max units dc characteristics rheostat mode specifications apply to all vrs resistor differential nl 2 r-dnl r wb , v a = nc C5 C1 +3 lsb resistor nonlinearity 2 r-inl r wb , v a = nc C4 1.5 +4 lsb nominal resistance 3 rt a = +25 c, model: ad840xyy1 0.8 1.2 1.5 k w resistance tempco d r ab / d tv ab = v dd , wiper = no connect 700 ppm/ c wiper resistance r w i w = 1 v/r ab 53 100 w nominal resistance match d r/r o ch 1 to 2, v ab = v dd , t a = +25 c 0.75 2 % dc characteristics potentiometer divider specifications apply to all vrs resolution n 8 bits integral nonlinearity 4 inl C6 2 +6 lsb differential nonlinearity 4 dnl v dd = +5 v C4 C1.5 +2 lsb dnl v dd = +3 v, t a = +25 c C5 C2 +5 lsb voltage divider temperature coefficent d v w / d t code = 80 h 25 ppm/ c full-scale error v wfse code = ff h C20 C12 0 lsb zero-scale error v wzse code = 00 h 0 6 10 lsb resistor terminals voltage range 5 v a, b, w 0v dd v capacitance 6 ax, bx c a, b f = 1 mhz, measured to gnd, code = 80 h 75 pf capacitance 6 wx c w f = 1 mhz, measured to gnd, code = 80 h 120 pf shutdown supply current 7 i dd_sd v a = v dd , v b = 0 v, shdn = 0 0.01 5 m a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = +5 v 50 100 w digital inputs & outputs input logic high v ih v dd = +5 v 2.4 v input logic low v il v dd = +5 v 0.8 v input logic high v ih v dd = +3 v 2.1 v input logic low v il v dd = +3 v 0.6 v output logic high v oh r l = 1 k w to v dd v dd C0.1 v output logic low v ol i ol = 1.6 ma, v dd = +5 v 0.4 v input current i il v in = 0 v or +5 v, v dd = +5 v 1 m a input capacitance 6 c il 5pf power supplies power supply range v dd range 2.7 5.5 v supply current (cmos) i dd v ih = v dd or v il = 0 v 0.01 5 m a supply current (ttl) 8 i dd v ih = 2.4 v or 0.8 v, v dd = +5.5 v 0.9 4 ma power dissipation (cmos) 9 p diss v ih = v dd or v il = 0 v, v dd = +5.5 v 27.5 m w power supply sensitivity pss d v dd = +5 v 10% 0.0035 0.008 %/% pss d v dd = +3 v 10% 0.05 0.13 %/% dynamic characteristics 6, 10 bandwidth C3 db bw_1k r = 1 k w 5,000 khz total harmonic distortion thd w v a = 1 v rms + 2 v dc, v b = 2 v dc, f = 1 khz 0.015 % v w settling time t s v a = v dd , v b = 0 v, 1% error band 0.5 m s resistor noise voltage e nwb r wb = 500 w , f = 1 khz, rs = 0 3 nv/ ? hz crosstalk 11 c t v a = v dd , v b = 0 v C65 db notes for 1 k w version 1 typicals represent average readings at +25 c and v dd = +5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. see figure 30 test circuit. i w = 500 m a for v dd = +3 v and i w = 4 ma for v dd = +5 v for 1 k w version. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see figure 29 test circuit. 5 resistor terminals a, b, w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on the measured terminal. the remaining resistor terminals are left open circuit. 7 measured at the ax terminals. all ax terminals are open circuited in shutdown mode. 8 worst case supply current consumed when input logic level at 2.4 v, standard characteristic of cmos logic. see figure 21 for a plot of i dd versus logic voltage. 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = +5 v. 11 measured at a v w pin where an adjacent v w pin is making a full-scale voltage change. specifications subject to change without notice. ad8400/ad8402/ad8403Cspecifications (v dd = +3 v 6 10% or + 5 v 6 10%, v a = +v dd , v b = 0 v, C40 8 c t a +85 8 c unless otherwise noted) C4C rev. b
all versions electrical characteristics parameter symbol conditions min typ 1 max units switching characteristics 2, 3 input clock pulse width t ch , t cl clock level high or low 10 ns data setup time t ds 5ns data hold time t dh 5ns clk to sdo propagation delay 4 t pd r l = 1 k w to +5 v, c l 20 pf 1 25 ns cs setup time t css 10 ns cs high pulse width t csw 10 ns reset pulse width t rs 50 ns clk fall to cs rise hold time t csh 0ns cs rise to clock rise setup t cs1 10 ns notes 1 typicals represent average readings at +25 c and v dd = +5 v. 2 guaranteed by design and not subject to production test. resistor-terminal capacitance tests are measured with 2.5 v bias on the measured terminal. the remaining resistor terminals are left open circuit. 3 see timing diagram for location of measured values. all input control voltages are specified with t r = t f = 1 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. switching characteristics are measured using v dd = +3 v or +5 v. to avoid false clocking a minimum input logic slew rate of 1 v/ m s should be maintained. 4 propagation delay depends on value of v dd , r l and c l Csee applications text. specifications subject to change without notice. ad8400/ad8402/ad8403Cspecifications warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8400/ad8402/ad8403 feature proprietary esd protection circuitry, perma- nent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. (v dd = +3 v 6 10% or + 5 v 6 10%, v a = +v dd , v b = 0 v, C40 8 c t a +85 8 c unless otherwise noted)
ad8400/ad8402/ad8403 C6C rev. b table i. serial data word format addr data b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb msb lsb 2 9 2 8 2 7 2 0 pin configurations 1 2 3 4 8 7 6 5 top view (not to scale) ad8400 b1 clk v dd w1 a1 gnd cs sdi 14 13 12 11 10 9 8 1 2 3 4 7 6 5 top view (not to scale) agnd v dd w1 a1 b1 b2 a2 w2 ad8402 sdi clk rs dgnd shdn cs 13 16 15 14 24 23 22 21 20 19 18 17 top view (not to scale) 12 11 10 9 8 1 2 3 4 7 6 5 ad8403 agnd2 agnd1 w1 a1 b1 b2 a2 w2 w3 a3 b3 agnd4 b4 a4 w4 dgnd shdn rs v dd agnd3 cs sdi clk sdo ordering guide #chs/ temperature package package model k v range description option* ad8400an10 x1/10 -40 c to +85 c pdip-8 n-8 AD8400AR10 x1/10 -40 c to +85 c so-8 so-8 ad8402an10 x2/10 -40 c to +85 c pdip-14 n-14 ad8402ar10 x2/10 -40 c to +85 c so-14 so-14 ad8402aru10 x2/10 -40 c to +85 c tssop-14 ru-14 ad8403an10 x4/10 -40 c to +85 c pdip-24 n-24 ad8403ar10 x4/10 -40 c to +85 c soic-24 sol-24 ad8403aru10 x4/10 -40 c to +85 c tssop-24 ru-24 ad8400an50 x1/50 -40 c to +85 c pdip-8 n-8 ad8400ar50 x1/50 -40 c to +85 c so-8 so-8 ad8402an50 x2/50 -40 c to +85 c pdip-14 n-14 ad8402ar50 x2/50 -40 c to +85 c so-14 so-14 ad8403an50 x4/50 -40 c to +85 c pdip-24 n-24 ad8403ar50 x4/50 -40 c to +85 c soic-24 sol-24 ad8400an100 x1/100 -40 c to +85 c pdip-8 n-8 AD8400AR100 x1/100 -40 c to +85 c so-8 so-8 ad8402an100 x2/100 -40 c to +85 c pdip-14 n-14 ad8402ar100 x2/100 -40 c to +85 c so-14 so-14 ad8402aru100 x2/100 -40 c to +85 c tssop-14 ru-14 ad8403an100 x4/100 -40 c to +85 c pdip-24 n-24 ad8403ar100 x4/100 -40 c to +85 c soic-24 sol-24 ad8403aru100 x4/100 -40 c to +85 c tssop-24 ru-24 ad8400an1 x1/1 -40 c to +85 c pdip-8 n-8 ad8400ar1 x1/1 -40 c to +85 c so-8 so-8 ad8402an1 x2/1 -40 c to +85 c pdip-14 n-14 ad8402ar1 x2/1 -40 c to +85 c so-14 so-14 ad8403an1 x4/1 -40 c to +85 c pdip-24 n-24 ad8403ar1 x4/1 -40 c to +85 c soic-24 sol-24 ad8403aru1 x4/1 -40 c to +85 c tssop-24 ru-24 *n = plastic dip; so = small outline; ru = thin shrink so. the ad8400, ad8402 and the ad8403 contain 720 transistors.
ad8400/ad8402/ad8403 rev. b C7C ad8400 pin descriptions pin name description 1 b1 terminal b rdac 2 gnd ground 3 cs chip select input, active low. when cs returns high data in the serial input register is loaded into the dac register. 4 sdi serial data input 5 clk serial clock input, positive edge triggered 6v dd positive power supply, specified for operation at both +3 v and +5 v. 7 w1 wiper rdac, addr = 00 2 8 a1 terminal a rdac ad8402 pin descriptions pin name description 1 agnd analog ground* 2 b2 terminal b rdac #2 3 a2 terminal a rdac #2 4 w2 wiper rdac #2, addr = 01 2 5 dgnd digital ground* 6 shdn terminal a open circuit. shutdown controls variable resistors #1 and #2 7 cs chip select input, active low. when cs returns high data in the serial input register is decoded based on the address bits and loaded into the target dac register. 8 sdi serial data input 9 clk serial clock input, positive edge triggered 10 rs active low reset to midscale; sets rdac registers to 80 h 11 v dd positive power supply, specified for operation at both +3 v and +5 v 12 w1 wiper rdac #1, addr = 00 2 13 a1 terminal a rdac #1 14 b1 terminal b rdac #1 *all agnds must be connected to dgnd. ad8403 pin descriptions pin name description 1 agnd2 analog ground #2* 2 b2 terminal b rdac #2 3 a2 terminal a rdac #2 4 w2 wiper rdac #2, addr = 01 2 5 agnd4 analog ground #4* 6 b4 terminal b rdac #4 7 a4 terminal a rdac #4 8 w4 wiper rdac #4, addr = 11 2 9 dgnd digital ground* 10 shdn active low input. terminal a open circuit. shutdown controls variable resistors #1 through #4 11 cs chip select input, active low. when cs returns high data in the serial input register is decoded based on the address bits and loaded into the target dac register. 12 sdi serial data input 13 sdo serial data output, open drain transistor requires pull-up resistor 14 clk serial clock input, positive edge triggered 15 rs active low reset to midscale; sets rdac registers to 80 h 16 v dd positive power supply, specified for operation at both +3 v and +5 v 17 agnd3 analog ground #3* 18 w3 wiper rdac #3, addr = 10 2 19 a3 terminal a rdac #3 20 b3 terminal b rdac #3 21 agnd1 analog ground #1* 22 w1 wiper rdac #1, addr = 00 2 23 a1 terminal a rdac #1 24 b1 terminal b rdac #1 *all agnds must be connected to dgnd.
code ?decimal 10 8 0 0 32 256 64 96 128 160 192 224 6 4 2 resistance ?k w v dd = +3v or +5v r wb r wa figure 2. wiper to end terminal resistance vs. code digital input code ?decimal 1 0.5 ? 0 32 256 64 96 128 160 192 224 0 ?.5 v dd = +5v t a = ?0 c t a = +25 c t a = +85 c r-inl error ?lsb figure 5. resistance step position nonlinearity error vs. code digital input code ?decimal 1 0.5 ? 0 32 256 64 96 128 160 192 224 0 ?.5 inl nonlinearity error ?lsb t a = ?0 c t a = +25 c t a = +85 c v dd = +5v figure 8. potentiometer divider nonlinearity error vs. code ad8400/ad8402/ad8403Ctypical performance characteristics i wa current ?ma 5 4 0 07 145 3 2 1 23 6 80 h 40 h 20 h ff h code = 10 h t a = +25 c v dd = +5v v wb voltage ?v 05 h figure 3. resistance linearity vs. conduction current wiper resistance ? w frequency 60 48 0 40.0 42.5 65.0 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 36 24 12 ss = 1205 units v dd = 4.5v t a = +25 c figure 6. 10 k w wiper-contact- resistance histogram wiper resistance ? w frequency 60 48 0 35 37 55 39 41 43 45 47 49 51 53 36 24 12 ss = 184 units v dd = 4.5v t a = +25 c figure 9. 50 k w wiper-contact- resistance histogram wiper resistance ? w frequency 60 48 0 40.0 42.5 65.0 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 36 24 12 ss = 184 units v dd = 4.5v t a = +25 c figure 4. 100 k w wiper-contact- resistance histogram temperature ? c nominal resistance ? w 10 8 0 ?5 ?0 125 ?5 0 25 50 75 100 6 4 2 r ab (end-to-end) r wb (wiper-to-end) code = 80 h figure 7. nominal resistance vs. temperature code ?decimal potentiometer mode tempco ?ppm/c 70 60 ?0 0 32 160 64 96 128 30 20 10 0 50 40 192 224 256 v dd = +5v t a = ?0 c/+85 c v a = 2.00v v b = 0v figure 10. d v wb / d t potentiometer mode tempco C8C rev. b
ad8400/ad8402/ad8403 rev. b C9C time = 5 m s/div figure 15. large signal settling time time 200ns/div figure 18. digital feedthrough vs. time frequency ?hz 6 0 ?4 gain ?db 10 1m 100 1k 10k 100k ? ?2 ?8 ?8 ?4 ?0 ?6 ?2 code = ff 80 40 20 10 08 04 02 01 t a = +25 c see test figure 33 figure 13. gain vs. frequency for r = 10 k w frequency ?hz gain ?db 0 ? ?8 1k 10k 1m ?0 ?6 ?2 ?2 ?4 ?8 ?4 100k 6 code = ff h 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h figure 16. 50 k w gain vs. fre- quency vs. code frequency ?hz gain ?db 0 ? ?8 1k 10k 1m ?0 ?6 ?2 ?2 ?4 ?8 ?4 100k code = ff h 6 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h figure 19. 100 k w gain vs. fre- quency vs. code output input v out (50mv/div) r w (20mv/div) cs (5v/div) code ?decimal 700 600 ?00 0 32 160 64 96 128 300 200 100 0 500 400 192 224 256 rheostat mode tempco ?ppm/c v dd = +5v t a = ?0 c/+85 c v a = no connect r wb measured figure 11. d r wb / d t rheostat mode tempco hours of operation at 150 c 0.75 0.5 ?.75 0 600 100 300 400 0.25 ?.25 ?.5 200 500 code = 80 h v dd = +5v ss = 158 units 0 d r wb resistance ?% avg + 2 sigma avg avg ?2 sigma figure 14. long-term drift accelerated by burn-in frequency ?hz thd + noise ?% 10 0.001 10 100k 100 1k 10k 1 0.1 filter = 22khz v dd = +5v t a = +25 c 0.01 see test circuit figure 32 see test circuit figure 31 figure 17. total harmonic distortion plus noise vs. frequency figure 12. one position step change at half-scale (code 7f h to 80 h ) time 500ns/div
ad8400/ad8402/ad8403 C10C rev. b frequency ?hz 10 10k 1m normalized gain flatness ?0.1db/div 100k 100 1k see test circuit 33 code = 80 h v dd = +5v t a = +25 c r = 10k w r = 50k w r = 100k w figure 20. normalized gain flat- ness vs. frequency frequency ?hz gain ?db 0 ? 1k 10k 1m ?0 ?6 ?2 ?2 ?4 ?8 100k v in = 100mv rms v dd = +5v r l = 1m w 6 12 f ?db = 125khz, r = 50k w f ?db = 700khz, r = 10k w f ?db = 71khz, r = 100k w figure 23. C3 db bandwidths frequency ?hz 100k 2m 200k 1m 0 ?0 ?0 0 ?5 ?0 400k 4m 6m phase ?degrees 10m gain ?db v dd = +5v t a = +25 c wiper set at half-scale 80 h figure 26. 1 k w gain and phase vs. frequency input logic voltage ?volts i dd ?supply current ?ma 10 1 0.01 05 1234 0.1 t a = +25 c v dd = +5v v dd = +3v figure 21. supply current vs. logic input voltage frequency ?hz 1k 1m 10m 10k 100k i dd ?supply current ?? 1200 1000 800 600 400 200 0 t a = +25 c a b c d a ?v dd = 5.5v code = 55 h b ?v dd = 3.3v code = 55 h c ?v dd = 5.5v code = ff h d ?v dd = 3.3v code = ff h figure 24. supply current vs. clock frequency i a shutdown current ?na 100 1 ?5 ?5 10 v dd = +5v ?5 5 25 45 65 85 105 125 temperature ? c figure 27. shutdown current vs. temperature frequency ?hz psrr ?db 80 0 100 1m 1k 10k 100k 60 40 v dd = +5v dc 1v p-p ac t a = +25 c code = 80 h c l = 10pf v a = 4v, v b = 0v 20 see test circuit figure 32 figure 22. power supply rejection vs. frequency v dd r on ? w 160 0 140 80 60 40 20 120 100 01 6 2345 t a = +25 c v dd = +2.7v v dd = +5.5v see test circuit figure 36 figure 25. ad8403 incremental wiper on resistance vs. v dd temperature ? c i dd ?supply current a 1 0.1 0.001 ?5 ?5 125 ?5 5 25 45 65 85 105 0.01 logic input voltage = 0, v dd v dd = +5.5v v dd = +3.3v figure 28. supply current vs. temperature
parametric test circuitsCad8400/ad8402/ad8403 v+ dut v ms a b w v+ = v dd 1lsb = v+/256 figure 29. potentiometer divider nonlinearity error test circuit (inl, dnl) dut v ms a b w no connect i w figure 30. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) i ms v w2 ?[v w1 + i w (r aw ii r bw )] i w v+ ? v dd where v w1 = v ms when i w = 0 and v w2 = v ms when i w = 1/r v+ dut v ms a b w v w i w = 1v/r nominal r w = figure 31. wiper resistance test circuit psrr (db) = 20log ( ? ) pss (%/%) = d v ms d v dd d v ms % d v dd % v+ = v dd 10% v+ v ms a b w v dd v a ~ figure 32. power supply sensitivity test circuit (pss, psrr) ab v in 2.5v dc op279 +5v v out ~ dut w offset gnd figure 33. inverting programmable gain test circuit ~ ab v in 2.5v op279 +5v v out dut w offset gnd figure 34. noninverting programmable gain test circuit ~ b a v in 2.5v +15v v out dut w ?5v offset gnd op42 figure 35. gain vs. frequency test circuit dut i sw b w ? 0 tov dd r sw = 0.1v i sw code = h 0.1v figure 36. incremental on resistance test circuit rev. b C11C
ad8400/ad8402/ad8403 C12C rev. b programming the variable resistor rheostat operation the nominal resistance of the vr (rdac) between terminals a and b are available with values of 1 k w , 10 k w , 50 k w and 100 k w . the final digits of the part number determine the nominal resis- tance value, e.g., 10 k w = 10; 100 k w = 100. the nominal resis- tance (r ab ) of the vr has 256 contact points accessed by the wiper terminal, plus the b terminal contact. the 8-bit data word in the rdac latch is decoded to select one of the 256 possible settings. the wipers first connection starts at the b terminal for data 00 h . this b terminal connection has a wiper contact resis- tance of 50 w . the second connection (10 k w part) is the first tap point located at 89 w [= r ba (nominal resistance)/256 + r w = 39 w + 50 w ] for data 01 h . the third connection is the next tap point representing 78 + 50 = 128 w for data 02 h . each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10011 w . the wiper does not di- rectly connect to the b terminal. see figure 37 for a simplified diagram of the equivalent rdac circuit. the ad8400 contains one rdac, the ad8402 contains two independent rdacs and the ad8403 contains four independent rdacs. the general transfer equation that determines the d igi- tally programmed output resistance between wx and bx is: r wb ( dx ) = ( dx )/256 r ba + r w equation 2 where dx is the data contained in the 8-bit rdac# latch, and r ba is the nominal end-to-end resistance. for example, when v b = 0 v and a terminal is open circuit, the following output resistance values will be set for the following rdac latch codes (applies to 10 k w potentiometers): dr wb (dec) ( w ) output state 255 10011 full scale 128 5050 midscale ( rs = 0 condition) 1 89 1 lsb 0 50 zero-scale (wiper contact resistance) note in the zero-scale condition a finite wiper resistance of 50 w is present. care should be taken to limit the current flow be- tween w and b in this state to a maximum value of 5 ma to avoid degradation or possible destruction of the internal switch contact. like the mechanical potentiometer the rdac replaces, it is to- tally symmetrical. the resistance between the wiper w and ter- minal a also produces a digitally controlled resistance r wa . when these terminals are used the b terminal should be tied to the wiper. setting the resistance value for r wa starts at a maxi- mum value of resistance and decreases as the data loaded in the rdac latch is increased in value. the general transfer equation for this operation is: r wa ( dx ) = (256C dx )/256 r ba + r w equation 3 operation the ad8400/ad8402/ad8403 provide a single, dual and quad channel, 256 position digitally controlled variable resistor (vr) device. changing the programmed vr settings is accomplished by clocking in a 10-bit serial data word into the sdi (serial data input) pin. the format of this data word is two address bits, msb first, followed by eight data bits, msb first. table i prov ides the serial register data word format. the ad8400/ ad8402 /ad8403 has the following address assignments for the addr decode, which determines the location of vr latch re- ceiving the serial register data in bits b7 through b0: vr# = a 1 2 + a 0 + 1 equation 1 the single-channel ad8400 requires a1 = a0 = 0. the dual- channel ad8402 requires a1 = 0. vr settings can be changed one at a time in random sequence. the serial clock running at 10 mhz makes it possible to load all 4 vrs in under 4 m s (10 4 100 ns) for the ad8403. the exact timing requirements are shown in figures 1a, 1b and 1c. the ad8402/ad8403 resets to midscale by asserting the rs pin, simplifying initial conditions at power up. both parts have a power shutdown shdn pin that places the vr in a zero power consumption state where terminals ax are open circuited and the wiper wx is connected to bx resulting in only leakage cur- rents being consumed in the vr structure. in shutdown mode the vr latch settings are maintained so that returning to opera- tional mode from power shutdown, the vr settings return to their previous resistance values. the digital interface is still ac- tive in shutdown, except that sdo is deactivated. code changes in the registers can be made that will produce new wiper posi- tions when the device is taken out of shutdown. d7 d6 d5 d4 d3 d2 d1 d0 rdac latch & decoder ax wx bx r s = r nominal /256 r s r s r s r s shdn figure 37. ad8402/ad8403 equivalent vr (rdac) circuit
ad8400/ad8402/ad8403 rev. b C13C where dx is the data contained in the 8-bit rdac# latch, and r ba is the nominal end-to-end resistance. for example, when v a = 0 v and b terminal is open circuit, the following output resistance values will be set for the following rdac latch codes (applies to 10 k w potentiometers): dr wa (dec) ( w ) output state 255 89 full scale 128 5050 midscale ( rs = 0 condition) 1 10011 1 lsb 0 10050 zero scale the typical distribution of r ba from channel-to-channel matches within 1%. however, device-to-device matching is process lot dependent having a 20% variation. the change in r ba with temperature has a positive 500 ppm/ c temperature coefficient. the wiper-to-end-terminal resistance temperature coefficient has the best performance over the 10% to 100% of adjustment range where the internal wiper contact switches do not contribute any significant temperature related errors. the graph in figure 11 shows the performance of r wb tempco vs. code, using the trimmer with codes below 32 results in the larger temperature coefficients plotted. programming the potentiometer divider voltage output operation the digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. for example, connecting a terminal to +5 v and b terminal to ground produces an output voltage at the wiper starting at zero volts up to 1 lsb less than +5 v. each lsb of voltage is equal to the voltage applied across terminal ab divided by the 256 position resolution of the potentiometer divider. the general equation defining the output voltage with respect to ground for any given input voltage applied to terminals ab is: v w ( dx ) = dx /256 v ab + v b equation 4 operation of the digital potentiometer in the divider mode re- sults in more accurate operation over temperature. here the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the temperature drift improves to 15 ppm/ c. at the lower wiper position settings, the potentiometer divider temperature coefficient increases due to the contributions of the cmos switch wiper resistance becoming an appreciable portion of the total resistance from terminal b to the wiper. see figure 10 for a plot of potentiometer tempco performance versus code setting. digital interfacing the ad8400/ad8402/ad8403 contains a standard spi com- patible three-wire serial input control interface. the three inputs are clock (clk), cs and serial data input (sdi). the positive- edge sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. for best re- sults use logic transitions faster than 1 v/ m s. standard logic families work well. if mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. the figure 38 block diagrams show more detail of the internal digital circuitry. when cs is taken active low, the clock loads data into the 10-bit serial register on each positive clock edge (see table ii). r dac lat #1 gnd a1 w1 b1 v dd ad8400 cs clk 8 d7 d0 en addr dec a1 a0 sdi di ser reg d0 d7 10-bit a. r dac lat #1 r agnd rs a1 w1 b1 v dd ad8402 cs clk 8 d7 d0 r dac lat #2 r a4 w4 b4 d7 d0 en addr dec a1 a0 sdi di 10-bit ser reg d0 shdn dgnd d7 b. r dac lat #1 r agnd rs a1 w1 b1 v dd ad8403 cs clk sdo 8 d7 d0 r dac lat #4 r a4 w4 b4 d7 d0 en addr dec a1 a0 d7 sdi do di ser reg d0 shdn dgnd c. figure 38. block diagrams
ad8400/ad8402/ad8403 C14C rev. b table ii. input logic control truth table clk cs rs shdn register activity l l h h no sr effect, enables sdo pin. p l h h shift one bit in from the sdi pin. the tenth previously entered bit is shifted out of the sdo pin. x p h h load sr data into rdac latch based on a1, a0 decode (table iii). x h h h no operation. x x l h sets all rdac latches to midscale, wiper centered, and sdo latch cleared. x h p h latches all rdac latches to 80 h . x h h l open circuits all resistor aCterminals, connects w to b, turns off sdo output transistor. note: p = positive edge, x = dont care, sr = shift register. the serial data-output (sdo) pin contains an open drain n- channel fet. this output requires a pull-up resistor in order to transfer data to the next packages sdi pin. the pull-up resistor termination voltage may be larger than the v dd supply (but less than max v dd of +8 v) of the ad8403 sdo output device, e.g., the ad8403 could operate at v dd = 3.3 v and the pull-up for interface to the next device could be set at +5 v. this allows for daisy chaining s everal rdacs from a single processor serial data line. the clock period needs to be increased when using a pull-up resistor to the sdi pin of the following device in the series. capacitive loading at the daisy chain node sdoCsdi between devices must be accounted for to successfully transfer data. when daisy chaining is used, the cs should be kept low until all the bits of every package are clocked into their respec- tive serial registers insuring that the address bits and data bits are in the proper decoding location. this would require 20 bits of address and data complying to the word format provided in table i if two ad8403 four-channel rdacs are daisy chained. note, only the ad8403 has a sdo pin. during shutdown shdn the sdo output pin is forced to the off (logic high state) to disable power dissipation in the pull up resistor. see figure 40 for equivalent sdo output circuit schematic. the data setup and data hold times in the specification table de- termine the data valid time requirements. the last 10 bits of the data word entered into the serial register are held when cs re- turns high. at the same time cs goes high it gates the address decoder, which enables one of the two (ad8402) or four (ad8403) positive edge triggered rdac latches. see figure 39 detail and table iii address decode table. table iii. address decode table a1 a0 latch decoded 0 0 rdac#1 0 1 rdac#2 1 0 rdac#3 ad8403 only 1 1 rdac#4 ad8403 only addr decode rdac 1 rdac 2 rdac 4 serial register ad8403 sdi clk cs figure 39. equivalent input control logic the target rdac latch is loaded with the last eight bits of the serial data word completing one dac update. in the case of the ad8403 four separate 10-bit data words must be clocked in to change all four vr settings. serial register sdi ck rs dq shdn cs clk rs sdo figure 40. detail sdo output schematic of the ad8403 all digital pins are protected with a series input resistor and par- allel zener esd structure shown in figure 41a. this structure applies to digital pins cs , sdi, sdo, rs , shdn , clk. the digital input esd protection allows for mixed power supply applications where +5 v cmos logic can be used to drive an ad8400/ad8402 or ad8403 operating from a +3 v power sup- ply. the analog pins a, b, w are protected with a 20 w series resistor and parallel zener, see figure 41b. 1k w digital pins logic figure 41a. equivalent esd protection circuits 20 w a, b, w figure 41b. equivalent esd protection circuit (analog pins) c w 120pf a b c a c b w c a = 90.4pf ?( ) + 30pf dw 256 rdac 10k w c b = 90.4pf ?(1 ? ) + 30pf dw 256 figure 42. rdac circuit simulation model for rdac = 10 k w
ad8400/ad8402/ad8403 rev. b C15C the ac characteristics of the rdacs are dominated by the inter- nal parasitic capacitances and the external capacitive loads. the C3 db bandwidth of the ad8403an10 (10 k w resistor) mea- sures 600 khz at half scale as a potentiometer divider. figure 23 provides the large signal bode plot characteristics of the three available resistor versions 10 k w , 50 k w , and 100 k w . the gain flatness versus frequency graph, figure 26, predicts filter appli- cations performance. a parasitic simulation model has been de- veloped, and is shown in figure 42. listing i provides a macro model net list for the 10 k w rdac: listing i. macro model net list for rdac .param dw=255, rdac=10e3 * .subckt dpot (a,w,) * ca a 0 {dw/256*90.4e-12+30e-12} raw a w {(1-dw/256)*rdac+50} cw w 0 120e-12 rbw w b {dw/256*rdac+50} cb b 0 {(1-dw/256)*90.4e-12+30e-12} * .ends dpot the total harmonic distortion plus noise (thd+n) is measured at 0.003% in an inverting op amp circuit using an offset ground and a rail-to-rail op279 amplifier, figure 33. thermal noise is primarily johnson noise, typically 9 nv/ ? hz for the 10 k w ver- sion at f = 1 khz. for the 100 k w device, thermal noise becomes 29 nv/ ? hz . channel-to-channel crosstalk measures less than C65 db at f = 100 khz. to achieve this isolation, the extra ground pins provided on the package to segregate the individual rdacs must be connected to circuit ground. agnd and dgnd pins should be at the same voltage potential. any unused potentio- meters in a package should be connected to ground. power sup- ply rejection is typically C35 db at 10 khz (care is needed to minimize power supply ripple in high accuracy applications). applications the digital potentiometer (rdac) allows many of the applica- tions of trimming potentiometers to be replaced by a solid-state solution offering compact size, freedom from vibration, shock and open contact problems encountered in hostile environ- ments. a major advantage of the digital potentiometer is its programmability. any settings can be saved for later recall in system memory. the two major configurations of the rdac include the potentiometer divider (basic 3-terminal application) and the rheostat (2-terminal configuration) connections shown in figures 29 and 30. certain boundary conditions must be satisfied for proper ad8400/ad8402/ad8403 operation. first, all analog signals must remain within the 0 to v dd range used to operate the single-supply ad8400/ad8402/ad8403 products. for standard potentiometer divider applications, the wiper output can be used directly. for low resistance loads, buffer the wiper with a suitable rail-to-rail op amp such as the op291 or the op279. second, for ac signals and bipolar dc adjustment applications, a virtual ground will generally be needed. whatever method is used to create the virtual ground, the result must provide the necessary sink and source current for all connected loads, in- cluding adequate bypass capacitance. figure 33 shows one channel of the ad8402 connected in an inverting program- mable gain amplifier circuit. the virtual ground is set at +2.5 v which allows the circuit output to span a 2.5 volt range with respect to virtual ground. the rail-to-rail amplifier capability is necessary for the widest output swing. as the wiper is adjusted from its midscale reset position (80 h ) toward the a terminal (code ff h ), the voltage gain of the circuit is increased in suc- cessfully larger increments. alternatively, as the wiper is ad- justed toward the b terminal (code 00 h ), the signal becomes attenuated. the plot in figure 43 shows the wiper settings for a 100:1 range of voltage gain (v/v). note the 10 db of pseudo- logarithmic gain around 0 db (1 v/v). this circuit is mainly useful for gain adjustments in the range of 0.14 v/v to 4 v/v; beyond this range the step sizes become very large and the resis- tance of the driving circuit can become a significant term in the gain equation. inverting gain ?v/v 256 128 0 0.1 1.0 10 96 64 32 160 192 224 digital code ?decimal figure 43. inverting programmable gain plot
ad8400/ad8402/ad8403 C16C rev. b active filter one of the standard circuits used to generate a low-pass, high- pass or bandpass filter is the state variable active filter. the digi- tal potentiometer allows full programmability of the frequency, gain and q of the filter outputs. figure 44 shows the filter cir- cuit using a +2.5 v virtual ground, which allows a 2.5 v p input and output swing. rdac2 and 3 set the lp, hp and bp cutoff and center frequencies respectively. these variable resistors should be programmed with the same data (as with ganged po- tentiometers) to maintain the best circuit q. figure 45 shows the measured filter response at the bandpass output as a func- tion of the rdac2 and rdac3 settings which produce a range of center frequencies from 2 khz to 20 khz. the filter gain re- sponse at the bandpass output is shown in figure 46. at a cen- ter frequency of 2 khz, the gain is adjusted over a C20 db to +20 db range determined by rdac1. circuit q is adjusted by rdac4. for more detailed reading on the state variable active filter, see analog devices application note, an-318. a1 a2 a3 a4 ~ 10k rdac4 10k rdac2 rdac3 0.01? 2.5v 0.01? rdac1 v in op279 2 high- pass low- pass band- pass b b b b figure 44. programmable state variable active filter frequency ?hz 40 20 ?0 20 100k 100 1k 10k 0 ?0 ?0 ?0 200k amplitude ?db ?.16 20.0000 k figure 45. programmed center frequency bandpass response frequency ?hz 40 20 ?0 20 100k 100 1k 10k 0 ?0 ?0 ?0 200k amplitude ?db ?9.01 2.00000 k figure 46. programmed amplitude bandpass response
ad8400/ad8402/ad8403 rev. b C17C outline dimensions dimensions shown in inches and (mm) 8-pin plastic dip (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 14-pin plastic dip package (n-14) 0.210 (5.33) max 0.160 (4.06) 0.115 (2.93) 0.795 (20.19) 0.725 (18.42) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc 0.070 (1.77) 0.045 (1.15) seating plane 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) min pin 1 0.280 (7.11) 0.240 (6.10) 7 8 14 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 14-pin narrow body soic package (so-14) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 pin 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 1 14 8 7 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) 0.3444 (8.75) 0.3367 (8.55) 0.0098 (0.25) 0.0040 (0.10) 14-lead tssop (ru-14) 14 8 7 1 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0
ad8400/ad8402/ad8403 C18C rev. b 24-pin narrow body plastic dip package (n-24) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.203) 0.195 (4.95) 0.115 (2.93) pin 1 0.280 (7.11) 0.240 (6.10) 24 1 13 12 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc 0.070 (1.77) 0.045 (1.15) seating plane 0.130 (3.30) min 1.275 (32.30) 1.125 (28.60) 0.015 (0.38) min 0.160 (4.06) 0.115 (2.92) 24-pin soic package (sol-24) 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 pin 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 13 12 1 24 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.1043 (2.65) 0.0926 (2.35) 0.6141 (15.60) 0.5985 (15.20) 0.0118 (0.30) 0.0040 (0.10) 24-lead thin surface mount tssop package (ru-24) 24 13 12 1 0.311 (7.90) 0.303 (7.70) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0
C19C
printed in u.s.a. c1997bC12C1/97 C20C

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